A field effect transistor having a fin structure (fin FET) is actively being developed. The fin FET has a fin-like projection perpendicular to a substrate surface, a gate insulator and agate electrode are formed on both side surfaces of the fin-like projection, and source/drain regions are formed on both sides of the gate.
In the fin FET, a channel surface is disposed perpendicular to the substrate surface, so that an occupied area may be reduced on the substrate. A cap layer is provided over a silicon layer of a Semiconductor On Insulator (SOI) substrate, and is patterned to form a silicon fin. The cap layer includes an oxide film or a lamination of the oxide film and a nitride film. In the SOI substrate, the silicon layer is disposed over an insulating film. After the gate insulator made of oxide silicon or nitride oxide silicon is formed over a fin surface, a polysilicon layer is deposited and patterned, and a gate electrode is formed. The fin regions on both sides of the gate electrode are doped to form a source/drain region.
FIG. 5 illustrates a configuration example of the fin FET. In FIG. 5, the silicon layer of the SOI substrate is patterned to form a fin 51 and contact regions 52 and 53. A cap layer 61 is left over the silicon layer. The oxide film or the nitride film is formed as a gate insulator 62 in the fin sidewall. A gate electrode 71 is formed so as to stride over the fin 51. A contact region 72 is formed in an end portion of the gate electrode 71. An impurity is added to the fin 51 by ion implantation to form the source/drain region. After a transistor structure is covered with an interlayer insulator, a contact hole reaching the contact regions 52 and 53 is made, and a conductive plug 80 such as a tungsten plug is made in the contact hole. The gate electrode 71 may be formed by laminating a polysilicon layer and a silicide layer, or may be formed by a metallic layer.
A channel of the fin FET is formed in the side surface of the fin. A channel length is determined by a width of the gate electrode. A channel width is determined by a fin height. For example, a fin length is determined by process accuracy. A narrow lead-out portion of the source/drain easily increases resistance of the source/drain. In another proposal, the fin is cut without extending an end portion thereof, and a metallic layer is embedded to form a Schottky contact.
When an opposite area between the gate electrode 71 and a semiconductor substrate disposed below the insulating film in the SOI substrate is enlarged, a parasitic capacitance of the gate electrode is increased which interrupts high-speed operation. In order to decrease the parasitic capacitance of the gate electrode, it is desirable to reduce the opposite area between the semiconductor substrate and the gate electrode.
There is also proposed a configuration in which the opposite area of the gate electrode is reduced with respect to the semiconductor substrate. In this method, an Si layer of the SOI substrate is etched with a hard mask to form the fin. After an oxide film liner and a nitride film liner are formed over the hard mask and the fin, the oxide film liner and the nitride film liner are covered with an insulating film. Chemical Mechanical Polishing (CMP) is performed to the insulating film until the nitride film liner is exposed, the insulating film is partially etched, and an upper surface of the insulating film is lowered below the nitride film liner. While an opposite portion of the substrate is left, the oxide film liner and the nitride film liner are etched to form a trench, a gate insulator is formed in the exposed Si fin surface, and a polysilicon gate electrode layer is embedded in the trench. The hard mask is exposed by CMP. The polysilicon gate electrode layer is left on the insulating film. A metal gate electrode layer is formed, and a gate etching mask is formed thereon. The metal gate electrode layer and the polysilicon gate electrode layer are etched with the gate etching mask to pattern the gate electrode. The ion implantation of the impurity is performed to the polysilicon gate electrode layer with a space interposed between the fin and the insulating film. The space is formed by the etching.
For example, Japanese Laid-Open Patent Publication Nos. 2002-289871 and 2005-150742 disclose a technique concerning the fin FET.